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ltm9013 1 9013f for more information www.linear.com/ltm9013 typical application features description 300mhz digital predistortion receiver the lt m ? 9013 is a 300mhz digital predistortion receiver. utilizing an integrated system in a package (sip) technol - ogy, it is a module ? (micromodule) receiver that includes a dual high speed 14-bit a/d converter, lowpass filter, differential gain stages and a quadrature demodulator. the ltm9013 is perfect for digital predistortion applica- tions, with ac performance that includes 59db snr and 1.3db frequency flatness from dc to 300mhz. a highpass filter or simple ac coupling are used external to the device for design flexiblity. the integrated on-chip broadband transformers provide a 50 single-ended interface at the rf input. a 5v supply powers the demodulator and a 3.3v supply powers the if amplifiers for minimal distortion. a 1.8v supply allows low power adc operation. a separate output supply allows the ddr lvds outputs to drive 1.8v logic. an optional multiplexer allows both channels to share a digital output bus. an optional clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles. 64k point fft f in = 1950mhz, C1dbfs applications n integrated i/q demodulator, if amplifier, and dual 14-bit, 310msps high speed adc n external highpass filter allows bandwidth adjustment n 300mhz lowpass filter for each channel n rf input frequency range: 0.7ghz to 4ghz n 50 single-ended rf port n 50 differential lo port n frequency flatness: 1.3db typical n 66dbc im3 level at C7dbfs n 59db snr at C1dbfs n parallel ddr lvds outputs n clock duty cycle stabilizer n low power: 2.6w n shutdown and nap modes n 15mm 15mm bga package n telecommunications n wideband, low if receivers n digital predistortion receivers n cellular base stations l , lt, ltc, ltm, module, linear technology and the linear logo are registered trademarks of linear technology corporation. v cc2 3.3v v cc1 5v gain_q 0.01f 0.01f 15nh 0.01f 0.01f 15nh gnd lo in 15nh 15nh 6.8pf 100 100 100 5v gain_i v dd 1.8v ltm9013 adc adc gnd 9013 ta01 clkout sdosdi sck cs adc clk ov dd 1.8v of 100 5v 6.8pf 0 90 par/ ser lna frequency (mhz) 0 amplitude (dbfs) ?60 ?40 ?20 0 128 9013 ta01b ?80 ?100 ?70 ?50 ?30 ?10 ?90 ?110 ?120 32 64 96 16 144 48 80 112 160
ltm9013 2 9013f for more information www.linear.com/ltm9013 pin configuration absolute maximum ratings supply voltage v cc1 ...................................................... C0.3v to 5.5v v cc2 ...................................................... C0.3v to 3.8v v dd , ov dd ............................................. C0.3v to 2.0v analog input voltage en, eip2, ref, ip2i, ip2q ........... C0.3v to v cc1 + 0.3v par/ ser , sense ..................... C0.3v to (v dd + 0.2v) digital input voltage (note 3) clk + , clk C ............................. C0.3v to (v dd + 0.3v) digital input voltage (note 4) cs , sdi, sck ......................................... C0.3v to 3.9v rf input dc voltage ............................................... 0.1v lo + , lo C input dc voltage ............. C0.3v to v cc1 + 0.3v analog input current +in_i, Cin_i, +in_q, Cin_q ............................ 20ma gain_i, gain_q, en_ i, en_ q, shdn_ i, shdn_ q ........................................................... 10ma lo + , lo C input power ........................................ +10dbm rf input power .................................................. +20dbm analog input power, continuous +in_i, Cin_i, +in_q, Cin_q ........................... +15dbm analog input power, 100s pulse +in_i, Cin_i, +in_q, Cin_q ........................... +20dbm analog output voltage +out_i, Cout_i, +out_q, Cout_q ......................... 2.5v to v cc1 + 0.3v digital output voltage sdo ..................................................... C0.3v to 3.9v except sdo ............................ C0.3v to (ov dd + 0.3v) operating temperature range ltm9013c ............................................... 0c to 70c ltm9013i ............................................. C40c to 85c storage temperature range .................. C55c to 125c caution: this part is sensitive to electrostatic discharge (esd). it is very important that proper esd precautions be observed when handling the rf and lo inputs of the ltm9013. (notes 1, 2) 1 a b c d e f g h j k l m n p 2 3 4 5 6 7 top view bga package 196-lead (15mm 15mm 2.82mm) 8 9 10 11 12 13 14 t jmax = 125c, v ja = 20c/w, v jcbottom = 6c/w, v jctop =19c/w, v jb =9c/w v values defined per jesd 51-12 weight = 1.35g
ltm9013 3 9013f for more information www.linear.com/ltm9013 electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. p rf = C5dbm, p lo = 0dbm (notes 5, 7) unless otherwise noted. order information lead free finish tray part marking* package description temperature range ltm9013cy-aa#pbf ltm9013cy-aa#pbf ltm9013y-aa 196-lead (15mm 15mm 2.8mm) bga 0c to 70c ltm9013iy-aa#pbf ltm9013iy-aa#pbf ltm9013y-aa 196-lead (15mm 15mm 2.8mm) bga C40c to 85c consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ this product is only offered in trays. for more information go to: http://www.linear.com/packaging/ symbol parameter conditions min typ max units rf input frequency range no external matching (mid band) with external matching (low band, high band) 1.5 to 2.7 0.7 to 4.0 ghz ghz lo input frequency range no external matching (mid band) with external matching (low band, high band) 1.5 to 2.7 0.7 to 4.0 ghz ghz if frequency range 0.5 to 300 mhz rf input return loss z o = 50, 1.5ghz to 2.7ghz, internally matched >10 db lo input return loss z o = 50, 1.5ghz to 2.7ghz, internally matched >10 db rf input power for C1dbfs rf = 2140mhz, lo = 1990mhz (figure 14) C5 dbm lo input power C6 to +6 dbm i/q gain mismatch rf = 2140mhz, lo = 1990mhz (figure 14) 0.15 db i/q phase mismatch rf = 2140mhz, lo = 1990mhz (figure 14) 1 deg lo to rf leakage lo = 1990mhz C55 dbm rf to lo isolation rf = 2140mhz 58 dbm gain flatness (notes 5, 6) f if = 500khz to 300mhz (figure 14) 0.5 db lowpass filter cutoff frequency 0.5db point 300 mhz resolution (no missing codes) l 14 bits integral linearity error (note 8) differential analog input 4.5 lsb differential linearity error differential analog input C1 0.35 1 lsb offset error (note 9) C186 62 186 lsb
ltm9013 4 9013f for more information www.linear.com/ltm9013 dynamic accuracy analog inputs and outputs the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. p rf = C5dbm, p lo = 0dbm (notes 5, 7) unless otherwise noted. the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (notes 5, 7) symbol parameter conditions min typ max units iip3 input 3rd order intercept, 1 tone rf = 2140mhz, lo = 1990mhz 30 dbm iip2 input 2nd order intercept, 1 tone rf = 2140mhz, lo = 1990mhz 56 dbm snr signal-to-noise ratio at C1dbfs rf = 2140mhz, lo = 1990mhz (figure 14) f if = 150mhz (note 6) l 59 59 62 dbfs dbfs sfdr spurious free dynamic range 2nd or 3rd harmonic rf = 2140mhz, lo = 1990mhz (figure 14) f if = 150mhz (note 6) l 60 65 70 db db spurious free dynamic range 4th or higher rf = 2140mhz, lo = 1990mhz (figure 14) f if = 150mhz (note 6) 75 80 db db s/(n+d) signal-to-noise plus distortion ratio rf = 2140mhz, lo = 1990mhz (figure 14) f if = 150mhz (note 6) l 58 58 61 dbfs dbfs imd3 intermodulation distortion at C7dbfs per tone rf = 2140mhz and 2141mhz, lo = 1990mhz (figure 14) 66 db symbol parameter conditions min typ max units demodulator adjust inputs (ip2i, ip2q) input voltage 0 1.3 v input impedance 2||1 k||pf settling time for step input; output with 90% of final value 2 s demodulator adjust input (ref) input voltage 0.4 0.5 0.7 v input impedance 8||1 m||pf amplifier analog inputs (+in_i, Cin_i, +in_q, Cin_q) differential input resistance v in(diff) = 100mv 49 57 65 input common mode voltage 640 mv minimum input frequency (3db corner) 500 khz amplifier gain control analog inputs (gain_i, gain_q) r in input resistance gain_i, gain_q = 1.0v, r in = 1v/?i il l 7.8 7.2 9.2 10.6 12.8 k k i il input low current gain_i, gain_q = 0v l C9 C10 C5 C1 C1 a a gain control range v gain = 0.2v to 1.2v l 27.5 29 30.5 db temperature coefficient of gain at fixed gain control voltage C0.007 db/c gain control slope gain control voltage = 0.2v to 1v, slope of the least-square fit line l 30.6 32.6 34.7 db/v average conformance error to gain slope line gain control voltage = 0.2v to 1v, standard error to the least-square fit line 0.12 db maximum conformance error to gain slope line gain control voltage = 0.2v to 1v, maximum error to the least-square fit line 0.2 db
ltm9013 5 9013f for more information www.linear.com/ltm9013 analog inputs and outputs digital inputs and outputs analog inputs and outputs the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (notes 5, 7) the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (notes 5, 7) symbol parameter conditions min typ max units adc analog inputs (sense) input leakage current 1.1v < sense < 1.2v C1 1 a demodulator analog outputs (+out_i, Cout_i, +out_q, Cout_q) common mode voltage v cc1 C 1.5v v differential output impedance 50||6 ||pf symbol parameter conditions min typ max units demodulator logic inputs (en, eip2) v ih high level input voltage v cc = 5v l 2 v v il low level input voltage v cc = 5v l 0.3 v input pull-up resistance v cc = 5v, v en = 4.4v to 2.6v 100 k eip2 input current eip2 = 5v 40 a turn-on time 0.2 s turn-off time 0.8 s i and q channel logic inputs (en_i, en_q, shdn_i, shdn_q) v ih high level input voltage v cc = 3.3v l 2.2 v v il low level input voltage v cc = 3.3v l 0.8 v input pull-up resistance v cc = 3.3v, v en_i,en_q = 0v to 0.5v 100 k input high current en_i, en_ q = 2.2v, shdn_i, shdn_q = 2.2v C30 C15 C1 a input low current en_i, en_ q = 0.8v, shdn_i, shdn_q = 0.8v C60 C30 C1 a adc encode clock inputs (clk + , clk C ) differential input voltage v dd = 1.8v l 0.2 v common mode input voltage internally set externally set l 1.1 1.2 1.5 v v input resistance 10 k input capacitance (note 10) 2 pf adc logic inputs (sdi, sck, cs) v ih high level input voltage v dd = 1.8v l 1.3 v v il low level input voltage v dd = 1.8v l 0.6 v input current v in = 0v to 3.6v l C10 10 a input capacitance (note 10) 3 pf adc logic inputs (par/ ser) input leakage current 0 < par/ ser < v dd C1 1 a adc logic output (sdo) logic low output resistance to gnd v dd = 1.8v, sdo = 0v 200 logic high output leakage current sdo = 0v to 3.6v l C10 10 a output capacitance (note 10) 4 pf
ltm9013 6 9013f for more information www.linear.com/ltm9013 digital inputs and outputs power requirements timing characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (notes 5, 7) the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (notes 5, 7) the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (notes 5, 7) symbol parameter conditions min typ max units data outputs (ov dd = 1.8v) differential output voltage 100 differential load, 3.5ma mode 100 differential load, 1.75ma mode l l 247 125 350 175 454 250 mv mv common mode output voltage 100 differential load, 3.5ma mode 100 differential load, 1.75ma mode l l 1.125 1.125 1.250 1.250 1.375 1.375 v v on-chip termination resistance termination enabled, ov dd = 1.8v 100 symbol parameter conditions min typ max units v cc1 demodulator and amplifier supply voltage l 4.75 5.25 v v cc2 amplifier analog supply voltage l 2.7 3.3 3.6 v v dd adc analog supply voltage l 1.74 1.8 1.9 v ov dd adc digital output supply voltage l 1.74 1.8 1.9 v i cc1 demodulator and amplifier supply current l 285 330 ma i cc1(shdn) demodulator and amplifier shutdown current en = 0v, en_i, en_ q = 3.3v, shdn_i, shdn_q = 0v l 16 20 ma i cc2 amplifier supply current l 132 160 ma i dd adc supply current l 335 385 ma i ovdd digital supply current 3.5ma mode 80 90 ma adc sleep power adc programmed for sleep mode, no clk 5 mw total power dissipation 2.6 w symbol parameter conditions min typ max units f s sampling frequency l 1 310 mhz t l clk low time duty cycle stabilizer off (note 10) duty cycle stabilizer on (note 10) l l 1.5 1.2 1.6 1.6 50 50 ns ns t h clk high time duty cycle stabilizer off (note 10) duty cycle stabilizer on (note 10) l l 1.5 1.2 1.6 1.6 50 50 ns ns t jitter sample-and-hold acquisition delay time jitter 0.15 ps rms t ap sample-and-hold acquisition delay time 1 ns data outputs (note 10) t d clk to data delay c l = 5pf l 1.7 2 2.3 ns t c clk to clkout delay c l = 5pf l 1.3 1.6 2 ns t skew data to clkout skew t d C t c l 0.3 0.4 0.55 ns
ltm9013 7 9013f for more information www.linear.com/ltm9013 timing characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (notes 5, 7) symbol parameter conditions min typ max units spi port timing (note 10) t sck sck period write mode readback mode c sdo = 20pf, r pullup = 2k l l 40 250 ns ns t s cs to sck set-up time 5 ns t h sck to cs hold time 5 ns t ds sdi set-up time 5 ns t dh sdi hold time 5 ns t do sck falling to sdo valid readback mode c sdo = 20pf, r pullup = 2k 125 ns note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all voltage values are with respect to ground with gnd and ognd wired together (unless otherwise noted). note 3: when these pin voltages are taken below gnd or above v dd , they will be clamped by internal diodes. this product can handle input currents of greater than 100ma below gnd or above v dd without latchup. note 4: when these pin voltages are taken below gnd they will be clamped by internal diodes. when these pin voltages are taken above v dd , they will not be clamped by internal diodes. this product can handle input currents of greater than 100ma below gnd without latchup. note 5: using test circuit 1 (see figure 14 design example in applications information section). note 6: signal applied to the inn pins and measures only the amplifier and adc. note 7: v cc1 = 5v, v cc2 = 3.3v, v dd = 1.8v, en = 5v, en_i, en _q = 0v, gain_i, gain_q = 1.2v, shdn_i, shdn _q = 3.3v, sense = 1.15v, f s = 310mhz, unless otherwise noted. note 8: integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. the deviation is measured from the center of the quantization band. note 9: dc offset is the adc output code with no rf or lo input signal applied the module. note 10: guaranteed by design, not subject to test
ltm9013 8 9013f for more information www.linear.com/ltm9013 typical performance characteristics hd2 at 150mhz if vs lo power hd2 at 150mhz if vs rf drive hd3 at 150mhz if vs rf drive im3 at 150mhz vs rf drive lo to rf isolation baseband frequency response 64k point fft, f in = 1925mhz, 1975mhz, C7dbfs per tone snr at 150mhz if vs rf drive baseband frequency (mhz) ?6 amplitude (db) ?4 ?2 0 ?5 ?3 ?1 100 200 300 400 9013 g01 500 500 150 250 350 450 frequency (mhz) 0 amplitude (dbfs) ?60 ?40 ?20 0 128 9013 g03 ?80 ?100 ?70 ?50 ?30 ?10 ?90 ?110 ?120 32 64 96 16 144 48 80 112 160 rf drive (dbm) ?5 58.0 snr (db) 58.5 59.0 59.5 60.0 60.5 61.0 0 5 10 15 9013 g04 lo power (dbm) ?22 ?80 hd2 (dbc) ?75 ?65 ?60 ?55 2 6 10 ?45 9013 g05 ?70 ?18 ?14 ?10 ?6 ?2 ?50 hd2, i channel hd2, q channel rf drive (dbm) ?5 ?70 hd2 (dbc) ?65 ?60 ?55 ?50 ?45 ?40 0 5 10 15 9013 g06 hd2, i channel hd2, q channel rf drive (dbm) ?5 ?55 ?50 ?40 10 9013 g07 ?60 ?65 0 5 15 ?70 ?75 ?45 hd3 (dbc) rf drive per tone (dbm) ?12 im3 (dbc) ?60 ?55 ?50 4 86 9013 g08 ?65 ?70 ?80 ?8 ?4 0 ?10 10 ?6 ?2 2 ?75 ?40 ?45 lo frequency (ghz) 1.5 isolation (db) ?40 ?30 ?20 2.3 2.4 9013 g09 ?50 ?60 ?80 1.7 1.9 2.1 1.6 2.5 1.8 2.0 2.2 ?70 0 ?10 frequency (mhz) 0 amplitude (dbfs) ?60 ?40 ?20 0 128 9013 g02 ?80 ?100 ?70 ?50 ?30 ?10 ?90 ?110 ?120 32 64 96 16 144 48 80 112 160 64k point fft, f in = 1950mhz, C1dbfs
ltm9013 9 9013f for more information www.linear.com/ltm9013 pin functions supply pins v cc1 (pin b7): analog 5v supply for demodulator and amplifiers. the specified operating range is 4.75v to 5.25v. the voltage on this pin provides power for the demodulator and amplifier stages only and is internally bypassed to gnd. v cc2 (pins a2, a3, a12, a13, d1, d12): analog 3.3v sup- ply for amplifiers. the specified operating range is 2.7v to 3.6v. v cc2 is internally bypassed to gnd. v dd (pins j6, j9): analog 1.8v supply for adc. the specified operating range is 1.74v to 1.9v. v dd is internally bypassed to gnd. ov dd (pins n5, n10): positive 1.8v supply for the digital output drivers. the specified operating range is 1.74v to 1.9v. ov dd is internally bypassed to gnd. gnd: analog ground. see pin configuration table for pin locations. analog inputs rf (pin a10): rf input pin. this is a single-ended 50 terminated input. no external matching network is required for the 1.5ghz to 2.7ghz band. an external series inductor (and/or shunt capacitor) may be required for impedance transformation to 50 in the band from 700mhz to 1.5ghz, or for the band from 2.7ghz to 4ghz (see figure 2). if the rf source is not dc blocked, a series blocking capacitor should be used. otherwise, damage to the ic may result. lo + , lo C (pins a6, a5): local oscillator input pins. this is a differential 50 terminated input. an external series induc - tor (and/or shunt capacitor) may be required for impedance transformation to 50 in the band from 700mhz to 1.5ghz, or for the band from 2.7ghz to 4ghz (see figure 4). if the lo source is not dc blocked, a series blocking capacitor must be used. otherwise, damage to the ic may result. +in_i, Cin_i (pins e10, e11): channel i signal input. this is a differential input that drives the amplifier. it has an internally generated dc bias. series blocking capacitors are required between these pins and +out_i, Cout_i. +in_q, Cin_q (pins e4, e5): channel q signal input. this is a differential input that drives the amplifier. it has an internally generated dc bias. series blocking capacitors are required between these pins and +out_q, Cout_q. gain_i (pin c12): i channel gain control input. this is an input that controls the gain of the amplifier. this pin is internally pulled low with 10k to gnd. the gain control slope is approximately 32db/v with a gain control range of 0.1v to 1.1v. gain_q (pin c1): q channel gain control input. this is an input that controls the gain of the amplifier. this pin is internally pulled low with 10k to gnd. the gain control slope is approximately 32db/v with a gain control range of 0.1v to 1.1v. clk + , clk C (pins j5, k5): adc clock input. conversion starts on the rising edge of clk + . ip2_i (pin c10): ip2 adjustment pin for i channel. ip2_q (pin d10): ip2 adjustment pin for q channel. ref (pin d8): voltage reference input for analog control voltage pins. sense (pin j8): adc reference programming pin. con - necting sense to v dd selects the internal reference and a 1.32v input range. analog outputs +out_i, Cout_i (pins f10, f11): channel i signal output. this is a differential output from the demodulator. the dc bias point is v cc1 C 1.5v for each pin. these pins must have an external 100 or inductor pull-up to v cc1 . series blocking capacitors are required between these pins and +in_i, Cin_i. +out_q, Cout_q (pins f4, f5): channel q signal output. this is a differential output from the demodulator. the dc bias point is v cc1 C 1.5v for each pin. these pins must have an external 100 or inductor pull-up to v cc1 . series blocking capacitors are required between these pins and +in_q, Cin_q. control pins en (pin b8): demodulator enable pin. if en = high (the input voltage is higher than 2.0v), the demodulator is en - abled. if en = low (the input voltage is less than 1.0v), it is disabled. if the enable function is not needed, then this pin should be tied to v cc1 . eip2 (pin d6): demodulator ip2 adjust enable pin. pin is internally pulled low with 200k to gnd. if eip2 = high
ltm9013 10 9013f for more information www.linear.com/ltm9013 pin functions (the input voltage is higher than 2.0v), the ip2 adjust circuit is enabled. if eip2 = low (the input voltage is less than 1.0v), it is disabled. nc1, nc2, nc3 (pins c6, c9, d9): do not connect. en_i (pin c14): first amplifier i channel enable pin. pin is internally pulled high with 100k to v cc2 . assert pin to a low voltage to enable the amplifier. connect pin to gnd if enable function is not used. en_q (pin c3): first amplifier q channel enable pin. pin is internally pulled high with 100k to v cc2 . assert pin to a low voltage to enable the amplifier. connect pin to gnd if enable function is not used. shdn_ i (pin d14): amplifier i channel shutdown pin. pin is internally pulled high with 100k to v cc2 . assert pin to a low voltage to shut down the amplifier. proper sequencing of the en_i and shdn_ i pins is required to avoid non-monotonic output signal behavior. connect pin to v cc2 if shutdown function is not used. shdn_ q (pin d3): amplifier q channel shutdown pin. pin is internally pulled high with 100k to v cc2 . assert pin to a low voltage to shut down the amplifier. proper sequencing of the en_q and shdn_q pins is required to avoid non-monotonic output signal behavior. connect pin to v cc2 if shutdown function is not used. sdi (pin k11): serial interface data input. in serial pro - gramming mode, (par/ ser = gnd), sdi is the serial interface data input. data on sdi is clocked into the mode control registers on the rising edge of sck. in the parallel programming mode (par/ ser = v dd ), sdi selects 3.5ma or a 7.5ma lvds output current (see table 4). sdi can be driven with 1.8v to 3.3v logic. sck (pin j11): serial interface clock input. in serial programming mode (par/ ser = gnd), sck is the serial interface clock input. in the parallel programming mode (par/ ser = v dd ), sck can be used to place the part in the low power sleep mode (see table 4). sck can be driven with 1.8v to 3.3v logic. cs (pin k10): serial interface chip select input. in serial programming mode (par/ ser = gnd), cs is the serial interface chip select input. when cs is low, sck is enabled for shifting data on sdi into the mode control registers. in the parallel programming mode (par/ ser = v dd ), cs controls the clock duty stabilizer (see table 4). cs can be driven with 1.8v to 3.3v logic. par/ ser (pin j10) : programming mode selection pin. connect to gnd to enable the serial programming mode where cs , sck, sdi, sdo become a serial interface that controls the adc operating modes. connect to v dd to enable the parallel programming mode where cs, sck, sdi, sdo become parallel logic inputs that control a reduced set of the adc operating modes. par/ ser should be connected directly to gnd or v dd and not be driven by a logic signal. digital outputs sdo (pin l11): serial interface data output. in serial pro - gramming mode (par/ ser = gnd), sdo is the optional serial inter-face data output. data on sdo is read back from the mode control registers and can be latched on the falling edge of sck. sdo is an open-drain n-channel mosfet output that requires an external 2k pull-up resistor from 1.8v to 3.3v. if readback from the mode control registers is not needed, the pull-up resistor is not necessary and sdo can be left unconnected. lvds digital outputs the following pins are differential lvds outputs. the output current level is programmable. there is an optional internal 100 termination resistor between the pins of each lvds output pair. clkout + , clkout C (pins p8, p7): adc data output clock. db0_1 C /db0_1 + to db12_13 C /db12_13 + (see pin con - figuration table for pin locations): q channel adc double data rate digital outputs. two data bits are multiplexed onto each differential output pair. the even data bits (db0, db2, db4, db6, db8, db10, db12) appear when clkout + is low. the odd data bits (db1, db3, db5, db7, db9, db11, db13) appear when clkout + is high. da0_1 C /da0_1 + to da12_13 C /da12_13 + (see pin con - figuration table for pin locations): q channel adc double data rate digital outputs. two data bits are multiplexed onto each differential output pair. the even data bits (da0, da2, da4, da6, da8, da10, da12) appear when clkout + is low. the odd data bits (da1, da3, da5, da7, da9, da11, da13) appear when clkout + is high. of + , of C (pins k2, k1): overflow/underflow outputs. of + is high when an overflow/underflow has occurred.
ltm9013 11 9013f for more information www.linear.com/ltm9013 figure 1. functional block diagram pin functions block diagram pin configuration 1 2 3 4 5 6 7 8 9 10 11 12 13 14 a gnd v cc2 v cc2 gnd lo C lo + gnd gnd gnd rf gnd v cc2 v cc2 gnd b gnd gnd gnd gnd gnd gnd v cc1 en gnd gnd gnd gnd gnd gnd c gain_q gnd en_q gnd gnd nc1 gnd gnd nc2 ip2_i gnd gain_i gnd en_i d v cc2 gnd shdn_q gnd gnd eip2 gnd ref nc3 ip2_q gnd v cc2 gnd shdn_i e gnd gnd gnd +in_q Cin_q gnd gnd gnd gnd +in_i Cin_i gnd gnd gnd f gnd gnd gnd +out_q Cout_q gnd gnd gnd gnd +out_i Cout_i gnd gnd gnd g gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd h gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd j gnd gnd gnd gnd clk + v dd gnd sense v dd par/ ser sck gnd gnd gnd k of C of + gnd gnd clk C gnd gnd gnd gnd cs sdi gnd gnd gnd l db01 C db01+ gnd gnd gnd gnd gnd gnd gnd gnd sdo gnd da1213 C da1213 + m db23 C db23 + db45 C db45 + gnd gnd gnd gnd gnd gnd da89 C da89 + da1011 C da1011 + n db67 C db67 + db89 C db89 + ov dd gnd gnd gnd gnd ov dd da45 C da45 + da67 C da67 + p gnd db1213 + db1213 C db1011 + db1011 C gnd clkout C clkout + gnd da23 + da23 C da01 + da01 C gnd top view of bga package (looking through component) v cc2 in_i + in_i ? da12_13 ov dd v dd ? ? ? ? ? ? da0_1 clkout + clkout ? db12_13 db0_1 9013 f01 of ? of + sense v cc1 out_i + out_i ? clock duty cycle control range select adc control sd0 sdi sck gain_i gain_q gnd clk ? clk + shdn_i en_i shdn_q en_q cs par/ ser ip2 control 0 rf 90 ip2_q ip2_i eip2 ref out_q + out_q ? lo ? lo + en in_q + in_q ?
ltm9013 12 9013f for more information www.linear.com/ltm9013 timing diagrams double-data rate output timing, all data are differential lvds t h t c t d t l of_a n-5 of_b n-5 of_a n-4 of_b n-4 of_a n-3 of_b n-3 t skew da0 n-5 da1 n-5 da0 n-4 da1 n-4 da0 n-3 da1 n-3 da12 n-5 da13 n-5 da12 n-4 da13 n-4 da12 n-3 da13 n-3 db0 n-5 db1 n-5 db0 n-4 db1 n-4 db0 n-3 db1 n-3 db12 n-5 db13 n-5 db12 n-4 db13 n-4 db12 n-3 db13 n-3 t ap n + 1 n + 2 n + 3 n clk ? clk + db0_1 + db0_1 ? da0_1 + da0_1 ? db12_13 + db12_13 ? da12_13 + da12_13 ? clkout + clkout ? of + of ? 9013 td01
ltm9013 13 9013f for more information www.linear.com/ltm9013 timing diagrams a6 t s t ds a5 a4 a3 a2 a1 a0 xx d7 d6 d5 d4 d3 d2 d1 d0 xx xx xx xx xx xx xx cs sck sdi r/w sdo high impedance spi port timing (readback mode) spi port timing (write mode) t dh t do t sck t h a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 9013 td02 cs sck sdi r/w sdo high impedance
ltm9013 14 9013f for more information www.linear.com/ltm9013 operation description the ltm9013 is a low if receiver targeting digital predistor - tion receiver applications, such as wireless infrastructure with rf input frequencies up to 4ghz. it is an integrated module receiver utilizing system in a package (sip) tech - nology to combine a dual, high speed 14-bit a/d converter, 300mhz lowpass filters, one low noise, differential amplifier per channel with adjustable gain and an i/q demodulator with ip2 adjustment. the following sections describe in further detail the opera - tion of each section. demodulator operation the rf signal is applied to the inputs of the rf trans - conductance amplifiers and is then demodulated into i/q baseband signals using quadrature lo signals which are internally generated from an external lo source by preci - sion 90 phase shifters. broadband transformers are integrated at the rf input to enable a single-ended rf interface. in the mid frequency band (1.5ghz to 2.7ghz), both rf and lo ports are inter - nally matched to 50. no external matching components are needed. for the low (700mhz to 1.5ghz), and high (2.7ghz to 4ghz) frequency bands a simple network with series inductors and/or shunt capacitors can be used as the impedance matching network. amplifier operation each channel of the ltm9013 consists of a single stage of ac-coupled, low noise and low distortion fully differential op amp/adc driver. each stage is followed by a 4-pole lowpass filter using a high speed, high performance operational amplifier and precision passive components. the stage is designed to provide maximum gain and phase flatness. the ltm9013 variable gain amplifer employs an interpo - lated, tapped attenuator circuit architecture to generate the variable-gain characteristic. the tapped attenuator is fed to a buffer and output amplifer to complete the differential signal path. this circuit architecture provides good rf input power handling capability along with a constant output noise and output ip3 characteristic that are desirable for most if signal chain applications. the internal control circuitry takes the gain control signal from the gain terminals and converts this to an appropriate set of control signals to the attenuator ladder. the attenuator control circuit ensures that the linear-in-db gain response is continuous and monotonic over the gain range for both slow and fast moving input control signals while exhibit - ing very little input impedance variation over gain. these design considerations result in a gain-vs-v g characteristic with a 0.1db ripple and a 0.5s gain response time that is slower than a similar digital step attenuator design. an often overlooked characteristic of an analog-controlled vga is upconverted amplitude modulation (am) noise from the gain control terminals. the vga behaves as a 2-quadrant multiplier, so some minimal care is required to avoid excessive am sideband noise generation. the following table demonstrates the effect of the baseline 20nv/ hz equivalent input control noise from the ltm9013 circuit along with the effect of a higher combined input noise due to a noisy external control circuit. control input total noise voltage (nv/ hz) peak am noise at 10khz offset near maximum gain (dbc/hz) 20 C142 40 C136 70 C131 100 C128 200 C122
ltm9013 15 9013f for more information www.linear.com/ltm9013 operation the baseline equivalent 20nv/ hz input noise is seen to produce worst-case am sidebands of C142dbc/hz which is near the C147dbm/hz output noise floor at maximum gain for a nominal 0dbm output signal. an input control noise voltage less than 80nv/ hz is generally recommended to avoid measurable am sideband noise. while op amp control circuit output noise voltage is usually below 80nv/ hz, some low power dac outputs exceed 150nv/ hz . dacs with output noise in the range of 100nv/ hz to 150nv/hz can usually be accommodated with a suitable 2:1 or 3:1 resistor divider network on the dac output to suppress the noise amplitude by the same ratio. noisy dacs in excess of 150nv/ hz should be avoided if minimal am noise is important in the application. adc input network the passive network between the amplifier output and the adc input stages provides a 0.1db ripple, 4th order chebyshev lowpass filter response. converter operation the ltm9013 includes a 2-channel, 14-bit 310msps a/d converter powered by a single 1.8v supply. the converter has five pipelined adc stages; a sampled input will result in a digitized value five cycles later. the analog inputs are driven differentially by the vga. the encode inputs should be driven differentially for optimal performance. the digital outputs are double data rate lvds. additional features can be chosen by programming the mode control registers through a serial spi port.
ltm9013 16 9013f for more information www.linear.com/ltm9013 applications information rf input figure 2 shows the mixers rf input which consists of an integrated transformer and high linearity transconduc - tance amplifiers. the primary side of the transformer is connected to the rf input pin. the secondary side of the transformer is connected to the differential inputs of the transconductance amplifiers. under no circumstances should an external dc voltage be applied to the rf input pin. dc current flowing into the primary side of the trans- former may cause damage to the integrated transformer. a series blocking capacitor should be used to ac-couple the rf input port to the rf signal source. figure 3. rf input return loss with external matching figure 2. rf input interface 9013 f02 external matching network for low band and mid band rf input rf c20 c21 c19 l5 to i-mixer ltm9013 to q-mixer the rf input port is internally matched over a wide fre - quency range from 1.5ghz to 2.7ghz with input return loss typically better than 10db. no external matching network is needed for this frequency range. when the part is operated at lower frequencies, however, the input return loss can be improved with the matching network shown in figure?2. shunt capacitors c20, c21 and series inductor l5 can be selected for optimum input impedance matching at the desired frequency as illustrated in figure?3. c19 serves as a series dc blocking capacitor. the rf input impedance and s11 parameters (without external matching components) are listed in table 1. frequency (mhz) 100 ?30 return loss (db) ?25 ?20 ?15 ?10 0 1000 10000 9013 f03 ?5 no matching elements 1.95ghz match (3.3nh + 1.5pf) table 1. rf input impedance frequency magnitude phase r x 500mhz 0.96 41.2 92.3 C95.4 600mhz 0.93 50.6 85.3 C62.0 700mhz 0.90 61.3 76.0 C36.0 800mhz 0.81 71.3 66.9 C17.6 900mhz 0.70 90.7 49.4 0.4 1000mhz 0.74 109.6 34.8 8.5 1100mhz 0.78 122.1 25.9 11.2 1200mhz 0.82 130.2 20.4 12.1 1300mhz 0.81 136.9 16.8 11.6 1400mhz 0.83 143.6 13.2 10.9 1500mhz 0.83 149.0 11.0 9.7 1600mhz 0.83 157.2 7.9 7.7 1700mhz 0.84 165.3 5.8 5.2 1800mhz 0.83 175.9 4.7 1.5 1900mhz 0.84 C173.1 4.8 C2.5 2000mhz 0.81 C161.6 7.3 C6.2 2100mhz 0.81 C150.2 10.9 C9.2 2200mhz 0.78 C141.5 15.2 C10.5 2300mhz 0.75 C132.7 20.2 C10.9 2400mhz 0.73 C129.9 22.2 C10.6 2500mhz 0.68 C126.8 24.9 C9.7 2600mhz 0.66 C128.6 24.3 C9.4 2700mhz 0.63 C129.1 24.8 C8.8 2800mhz 0.62 C126.9 26.0 C8.6 2900mhz 0.61 C124.9 27.2 C8.5 3000mhz 0.59 C117.7 31.5 C7.6
ltm9013 17 9013f for more information www.linear.com/ltm9013 applications information lo input port the mixers lo input interface is shown in figure 4. the input consists of a precision quadrature phase shifter which generates 0 and 90 phase-shifted lo signals for the lo buffer amplifiers driving the i/q mixers. under no circumstances should an external dc voltage be applied to the input pin. dc current flowing into the primary side of the transformer may damage the transformer. figure 5. lo input return loss with external matching figure 4. lo input interface lo input 9013 f04 lo+ lo? ltm9013 c22 c24 t1 lo quadrature generator and buffer amplifiers the lo input port is internally matched over a wide fre - quency range from 1.5ghz to 2.7ghz with input return loss typically better than 10db. no external matching network is needed for this frequency range. the lo input impedance and s11 parameters (without external matching components) are listed in table 2. outside this frequency range, the impedance match can be improved using series capacitor c22 and shunt capacitor c24. frequency (mhz) 100 ?30 return loss (db) ?25 ?20 ?15 ?10 0 1000 10000 9013 f05 ?5 no matching elements 1.8ghz match (0.5pf + 6.8nh) table 2. lo input impedance frequency magnitude phase r x 500mhz 0.71 C70.3 67.7 15.5 600mhz 0.66 C83.9 55.0 3.6 700mhz 0.66 C97.1 44.5 C3.3 800mhz 0.62 C119.8 29.8 C8.3 900mhz 0.55 C144.9 20.2 C6.5 1000mhz 0.51 C177.8 16.1 C0.4 1100mhz 0.48 146.5 22.2 5.3 1200mhz 0.52 115.0 34.3 6.1 1300mhz 0.57 87.9 51.6 C0.9 1400mhz 0.62 70.5 66.9 C12.4 1500mhz 0.66 55.0 84.7 C30.5 1600mhz 0.67 44.0 101.4 C46.6 1700mhz 0.69 34.1 123.7 C67.4 1800mhz 0.67 24.3 154.8 C75.6 1900mhz 0.66 15.5 193.5 C70.8 2000mhz 0.61 2.5 206.9 C10.8 2100mhz 0.55 C10.2 163.1 24.2 2200mhz 0.46 C34.3 101.7 21.3 2300mhz 0.34 C63.8 65.5 5.5 2400mhz 0.30 C113.3 40.0 C2.5 2500mhz 0.33 C164.3 25.8 C1.6 2600mhz 0.42 164.8 21.4 2.2 2700mhz 0.51 140.5 23.1 6.3 2800mhz 0.53 120.3 31.4 6.7 2900mhz 0.52 101.7 42.2 3.6 3000mhz 0.33 98.1 45.9 1.3
ltm9013 18 9013f for more information www.linear.com/ltm9013 applications information im2 adjustment circuitry the ltm9013 also contains circuitry for the independent adjustment of im2 levels on the i and q channels. when the eip2 pin is a logic high, this circuitry is enabled and the ip2i and ip2q analog control voltage inputs are able to adjust the im2 level. the im2 level can be effectively minimized over a large range of the baseband bandwidth. the circuitry has an effective baseband frequency upper limit of about 200mhz. any im2 component that falls in this frequency range can be minimized. variable gain amplifier the ltm9013 includes a high linearity, fully-differential analog-controlled variable-gain amplifier (vga) opti - mized for application frequencies in the range of 1mhz to 500mhz. the vga architecture provides a constant oip3 and constant output noise level (nf + gain) over the 31db gain-control range and thus exhibits a uniform spurious- free dynamic range (sfdr) over gain. this constant sfdr characteristic is ideal for use in receiver if chains. gain characteristics the ltm9013 provides a continuously adjustable gain of 31db that is linear-in-db with respect to the control volt - ages applied to gain_i and gain_q. in this way, a positive gain-control slope is easily achieved: apply gain control voltage to the gain_i/gain_q pins. gain increases with increasing gain_i/gain_q voltage. when connected in this typical single-ended configuration, the active control input range extends from 0.1v to 1.1v. this control input range can be extended using a resistor divider with a suitably low output resistance. for example, two series resistors of 1k each would extend the control input range from 0.2v to 2.2v while providing an effective 500 thevinin equivalent source resistance, a relatively small loading effect compared to the 10k input resistance of the gain_i/gain_q terminals. if input port characteristics the amplifier inputs provide a nominal 50 differential input impedance over the operating frequency range. the input impedance characteristic derives from the dif - ferential attenuator ladder. the internal circuit controls the if connections to this attenuator ladder and generates the appropriate common mode dc voltage. enable/shutdown both the en and shdn pins are self-biased to v cc2 through their respective 100k pull-up resistors, so the default open-pin state is powered on with the output amplifier signal path disabled. pulling the en pin low completes the signal path from the attenuator ladder through the output amplifier. the en pin essentially provides a fast muting function while the shdn pin provides slower power on/ off function. for applications requiring the shdn function, it is recom - mended that the output amplifier signal path be disabled with a high en voltage before transitioning the shdn signal. when enabling the amplifier, allow at least 5ms dwell time between the rising shdn transition and the falling en transition to avoid non-monotonic output signal behavior though the vga. the opposite delay sequence is recommended for the falling shdn transition, but this is less critical as the output signal amplitude will drop abruptly regardless of the en pin. figure 6 shdn en t dwell t dwell 9013 f06
ltm9013 19 9013f for more information www.linear.com/ltm9013 applications information esd the amplifier inputs are protected with reverse-biased esd diodes on all pins. if any pin is forced one diode drop above the positive supply or one diode drop below the negative supply, then large currents may flow through the diodes. no damage to the devices will occur if the current is kept below 10ma. reference the ltm9013 has an internal 1.25v voltage reference for the adc. for a 1.32v input range with internal reference, connect sense to v dd . for a 1.32v input range with an external reference, apply a 1.25v reference voltage to sense (figure? 7). apply a 1.15v reference voltage to sense to achieve specified performance. figure 7. reference circuit figure 8. equivalent encode input circuit encode input the signal quality of the encode inputs strongly affects the a/d noise performance. the encode inputs should be treated as analog signalsdo not route them next to digital traces on the circuit board. the encode inputs are internally biased to 1.2v through 10k equivalent resistance (figure 8). if the common mode of the driver is within 1.1v to 1.5v, it is possible to drive the encode inputs directly. otherwise a transformer or coupling capacitors are needed (figures 9 and 10). the maximum (peak) voltage of the input signal should never exceed v dd + 0.1v or go below C0.1v. scaler/ buffer v ref 0.1f sense 1.25v ltm9013 9013 f07 5 adc reference sense detector v dd ltm9013 9013 f08 1.2v 10k clk + clk ?
ltm9013 20 9013f for more information www.linear.com/ltm9013 applications information clock duty cycle stabilizer for good performance the encode signal should have a 50% (5%) duty cycle. if the optional clock duty cycle stabilizer circuit is enabled, the encode duty cycle can vary from 30% to 70% and the duty cycle stabilizer will maintain a constant 50% internal duty cycle. the duty cycle stabilizer is enabled via spi register a2 (see table 5) or by cs in parallel programming mode. for applications where the sample rate needs to be changed quickly, the clock duty cycle stabilizer can be disabled. in this cases care should be taken to make the clock a 50% ( 5%) duty cycle. digital outputs the digital outputs are double data rate lvds signals. two data bits are multiplexed and output on each differential output pair. there are seven lvds output pairs for chan - nel a (da0_1 + /da0_1 C through da12_13 C /da12_13 + ) and seven pairs for channel b (db0_1 + /db0_1 C through db12_13 C /db12_13 + ). overflow (of + /of C ) and the data output clock (clkout + /clkout C ) each have an lvds output pair. note that overflow for both channels is mul - tiplexed onto the of + /of C output pair. by default the outputs are standard lvds levels: 3.5ma output current and a 1.25v output common mode volt - age. an external 100? differential termination resistor is required for each lvds output pair. the termination resistors should be located as close as possible to the lvds receiver. programmable lvds output current the default output driver current is 3.5ma. this current can be adjusted by serially programming mode control register a3 (see table 5). available current levels are 1.75ma, 2.1ma, 2.5ma, 3ma, 3.5ma, 4ma and 4.5ma. figure 9. sinusoidal encode circuit ltm9013 v dd 9013 f09 1.2v 10k 50 100 50 0.1f 0.1f t1: macom etc1-1-13 figure 10. pecl or lvds encode drive v dd ltm9013 pecl or lvds input 9013 f10 1.2v 10k 100 0.1f 0.1f clk + clk ?
ltm9013 21 9013f for more information www.linear.com/ltm9013 clkout + d0-d13, of phase shift 0 45 90 135 180 225 270 315 clkinv 0 0 0 0 1 1 1 1 clkphase1 mode control bits 0 0 1 1 0 0 1 1 clkphase0 0 1 0 1 0 1 0 1 9013 f11 clk + applications information optional lvds driver internal termination in most cases, using just an external 100? termination resistor will give excellent lvds signal integrity. in addi - tion, an optional internal 100? termination resistor can be enabled by serially programming mode control register a3. the internal termination helps absorb any reflections caused by imperfect termination at the receiver. when the internal termination is enabled, the output driver current is doubled to maintain the same output voltage swing. overflow bit the overflow output bit (of) outputs a logic high when the analog input is either overranged or underranged. the overflow bit has the same pipeline latency as the data bits. the of output is double data rate; when clkout + is low, channel as overflow is available; when clkout + is high, channel bs overflow is available. phase shifting the output clock to allow adequate set-up and hold time when latching the output data, the clkout + signal may need to be phase shifted relative to the data output bits. most fpgas have this feature; this is generally the best place to adjust the timing. alternatively, the adc can also phase shift the clkout + / clkout C signals by serially programming mode control register a2. the output clock can be shifted by 0, 45, 90, or 135. to use the phase shifting feature the clock duty cycle stabilizer must be turned on. another con - trol register bit can invert the polarity of clkout + and clkout C , independently of the phase shift. the combina - tion of these two features enables phase shifts of 45 up to 315 (figure 11). figure 11. phase shifting clkout
ltm9013 22 9013f for more information www.linear.com/ltm9013 applications information data format table 3 shows the relationship between the analog input voltage, the digital data output bits and the overflow bit. by default the output data format is offset binary. the 2s complement format can be selected by serially program - ming mode control register a4. table 3. output codes vs input level +in C Cin of d13-d0 (offset binary) d13-d0 (2s complement) +overflow +full scale 1 0 0 11 1111 1111 1111 11 1111 1111 1111 11 1111 1111 1110 01 1111 1111 1111 01 1111 1111 1111 01 1111 1111 1110 mid-scale 0 0 0 0 10 0000 0000 0001 10 0000 0000 0000 01 1111 1111 1111 01 1111 1111 1110 00 0000 0000 0001 00 0000 0000 0000 11 1111 1111 1111 11 1111 1111 1110 Cfull scale Coverflow 0 0 1 00 0000 0000 0001 00 0000 0000 0000 00 0000 0000 0000 10 0000 0000 0001 10 0000 0000 0000 10 0000 0000 0000 digital output randomizer interference from the a/d digital outputs is sometimes unavoidable. digital interference may be from capacitive or inductive coupling or coupling through the ground plane. even a tiny coupling factor can cause unwanted tones in the adc output spectrum. by randomizing the digital output before it is transmitted off chip, these unwanted tones can be randomized which reduces the unwanted tone amplitude. the digital output is randomized by applying an exclu - sive - or logic operation between the lsb and all other data output bits. to decode, the reverse operation is appliedan exclusive-or operation is applied between the lsb and all other bits. the lsb, of and clkout out - puts are not affected. the output randomizer is enabled by serially programming mode control register a4. figure 12. functional equivalent of digital output randomizer figure 13. decoding a randomized digital output signal clkout clkout of d13/d0 d12/d0 ? ? ? d1/d0 d0 9013 f12 of d13 d12 d1 d0 randomizer on d13 fpga pc board d12 ? ? ? d1 d0 9013 f13 d0 d1/d0 d12/d0 d13/d0 of clkout ltm9013
ltm9013 23 9013f for more information www.linear.com/ltm9013 applications information alternate bit polarity another feature that may reduce digital feedback on the circuit board is the alternate bit polarity mode. when this mode is enabled, all of the odd bits (d1, d3, d5, d7, d9, d11, d13) are inverted before the output buffers. the even bits (d0, d2, d4, d6, d8, d10, d12), of and clkout are not affected. this can reduce digital currents in the circuit board ground plane and reduce digital noise, particularly for very small analog input signals. the digital output is decoded at the receiver by inverting the odd bits (d1, d3, d5, d7, d9, d11, d13.) the alternate bit polarity mode is independent of the digital output ran - domizereither both or neither function can be on at the same time. the alternate bit polarity mode is enabled by serially programming mode control register a4. digital output test patterns to allow in-circuit testing of the digital interface to the a/d, there are several test modes that force the a/d data outputs (of, d13 to d0) to known values: all 1s: all outputs are 1 all 0s: all outputs are 0 alternating: outputs change from all 1s to all 0s on alternating samples checkerboard: outputs change from 101010101010101 to 010101010101010 on alternating samples. the digital output test patterns are enabled by serially programming mode control register a4. when enabled, the test patterns override all other formatting modes: 2s complement, randomizer, alternate-bit polarity. output disable the digital outputs may be disabled by serially program - ming mode control register a3. all digital outputs includ - ing of and clkout are disabled. the high impedance disabled state is intended for long periods of inactivity, it is not designed for multiplexing the data bus between multiple converters. sleep mode the a/d may be placed in sleep mode to conserve power. in sleep mode the entire a/d converter is powered down, resulting in <5mw power consumption. if the encode input signal is not disabled the power consumption will be higher (up to 5mw at 250msps). sleep mode is enabled by mode control register a1 (serial programming mode), or by sck (parallel programming mode). in the serial programming mode it is also possible to dis - able channel b while leaving channel a in normal operation. the amount of time required to recover from sleep mode depends on the size of the bypass capacitor on v ref . with the 2.2f value used internally, the a/d will stabilize after 0.1ms + 2500 ? t p where t p is the period of the sampling clock. nap mode in nap mode the a/d core is powered down while the inter - nal reference circuits stay active, allowing faster wakeup. recovering from nap mode requires at least 100 clock cycles. nap mode is enabled by power-down register a1 in the serial programming mode. wake-up time from nap mode is guaranteed only if the clock is kept running, otherwise power-down wake-up conditions apply.
ltm9013 24 9013f for more information www.linear.com/ltm9013 applications information device programming modes the operating modes of the a/d can be programmed by either a parallel interface or a simple serial interface. the serial interface has more flexibility and can program all available modes. the parallel interface is more limited and can only program some of the more commonly used modes. parallel programming mode to use the parallel programming mode, par/ ser should be tied to v dd . the cs , sck and sdi pins are binary logic inputs that set certain operating modes. these pins can be tied to v dd or ground, or driven by 1.8v, 2.5v, or 3.3v cmos logic. table 4 shows the modes set by cs, sck and sdi. table 4. parallel programming mode control bits (par/ ser = v dd ) pin description cs clock duty cycle stabilizer control bit 0 = clock duty cycle stabilizer off 1 = clock duty cycle stabilizer on sck power down control bit 0 = normal operation 1 = sleep mode (entire adc is powered down) sdi lvds current selection bit 0 = 3.5ma lvds current mode 1 = 1.75ma lvds current mode serial programming mode to use the serial programming mode, par/ ser should be tied to ground. the cs, sck, sdi and sdo pins become a serial interface that program the a/d control registers. data is written to a register with a 16-bit serial word. data can also be read back from a register to verify its contents. serial data transfer starts when cs is taken low. the data on the sdi pin is latched at the first sixteen rising edges of sck. any sck rising edges after the first sixteen are ignored. the data transfer ends when cs is taken high again. the first bit of the 16-bit input word is the r/ w bit. the next seven bits are the address of the register (a6:a0). the final eight bits are the register data (d7:d0). if the r/w bit is low, the serial data (d7:d0) will be writ - ten to the register set by the address bits (a6:a0). if the r/w bit is high, data in the register set by the address bits (a6:a0) will be read back on the sdo pin (see the timing diagrams). during a readback command the register is not updated and data on sdi is ignored. the sdo pin is an open-drain output that pulls to ground with a 200? impedance. if register data is read back through sdo, an external 2k pull-up resistor is required. if serial data is only written and readback is not needed, then sdo can be left floating and no pull-up resistor is needed. table 5 shows a map of the mode control registers. software reset if serial programming is used, the mode control registers should be programmed as soon as possible after the power supplies turn on and are stable. the first serial command must be a software reset which will reset all register data bits to logic 0. to perform a software reset it is neces - sary to write 1 in register a0 (bit d7). after the reset is complete, bit d7 is automatically set back to zero. this register is write-only.
ltm9013 25 9013f for more information www.linear.com/ltm9013 table 5. serial programming mode register map (par/ ser = gnd). x indicates unused bit register a0: reset register (address 00h) write only d7 d6 d5 d4 d3 d2 d1 d0 reset x x x x x x x bit 7 reset software reset bit 0 = reset disabled 1 = software reset. all mode control registers are reset to 00h. this bit is automatically set back to zero after the reset is complete. bits 6-0 unused bits register a1: power-down register (address 01h) d7 d6 d5 d4 d3 d2 d1 d0 x x x x sleep nap pdb 0 bits 7-4 unused, this bit read back as 0 bit 3 sleep 0 = normal operation 1 = power down entire adc bit 2 nap 0 = normal mode 1 = low power mode for both channels bit 1 pdb 0 = normal operation 1 = power down channel b. channel a operates normally. bit 0 must be set to 0 register a2: timing register (address 02h) d7 d6 d5 d4 d3 d2 d1 d0 x x x x clkinv clkphase1 clkphase0 dcs bits 7-4 unused, this bit read back as 0 bit 3 clkinv output clock invert bit 0 = normal clkout polarity (as shown in the timing diagrams) 1 = inverted clkout polarity bits 2-1 clkphase1:clkphase0 output clock phase delay bits 00 = no clkout delay (as shown in the timing diagrams) 01 = clkout + /clkout C delayed by 45 (clock period ? 1/8) 10 = clkout + /clkout C delayed by 90 (clock period ? 1/4) 11 = clkout + /clkout C delayed by 135 (clock period ? 3/8) note: if the clkout phase delay feature is used, the clock duty cycle stabilizer must also be turned on. bit 0 dcs clock duty cycle stabilizer bit 0 = clock duty cycle stabilizer off 1 = clock duty cycle stabilizer on applications information
ltm9013 26 9013f for more information www.linear.com/ltm9013 register a3: output mode register (address 03h) d7 d6 d5 d4 d3 d2 d1 d0 x x x ilvds2 ilvds1 ilvds0 termon outoff bits 7-5 unused, this bit read back as 0 bits 4-2 ilvds2:ilvds0 lvds output current bits 000 = 3.5ma lvds output driver current 001 = 4.0ma lvds output driver current 010 = 4.5ma lvds output driver current 011 = not used 100 = 3.0ma lvds output driver current 101 = 2.5ma lvds output driver current 110 = 2.1ma lvds output driver current 111 = 1.75ma lvds output driver current bit 1 termon lvds internal termination bit 0 = internal termination off 1 = internal termination on. lvds output driver current is 2 the current set by ilvds2:ilvds0 bit 0 outoff digital output mode control bits 0 = digital outputs are enabled 1 = digital outputs are disabled (high impedance) register a4: data format register (address 04h) d7 d6 d5 d4 d3 d2 d1 d0 outtest2 outtest1 outtest0 abp 0 dteston rand twoscomp bits 7-5 outtest2:outtest0 digital output test pattern bits 000 = all digital outputs = 0 001 = all digital outputs = 1 010 = alternating output pattern. of, d13-d0 alternate between 000 0000 0000 0000 and 111 1111 1111 1111 100 = checkerboard output pattern. of, d13-d0 alternate between 101 0101 0101 0101 and 010 1010 1010 1010 note 1: other bit combinations are not used. note 2: patterns from channel a and channel b may not be synchronous. bit 4 abp alternate bit polarity mode control bit 0 = alternate bit polarity mode off 1 = alternate bit polarity mode on bit 3 must be set to 0 bit 2 dteston enable the digital output test patterns (set by bits 7-5) 0 = normal mode 1 = enable the digital output test patterns bit 1 rand data output randomizer mode control bit 0 = data output randomizer mode off 1 = data output randomizer mode on bit 0 twoscomp twos complement mode control bit 0 = offset binary data format 1 = twos complement data format applications information
ltm9013 27 9013f for more information www.linear.com/ltm9013 applications information design examples the ltm9013 allows the user to tailor the highpass corner frequency to suit the application. the 0.5db lowpass corner is set by the internal network at 300mhz. by cascading the external highpass and internal lowpass networks a bandpass characteristic is realized. an example of a very low frequency highpass corner is shown in figure 14. the typical performance for the overall module is shown below: if passband (1.5db): 1mhz to 300mhz rf input for C1dbfs: C5dbm at maximum gain snr at C1dbfs: 59.1db hd2 at C1dbfs: 74dbc imd3 at C7dbfs per tone: C72dbc the frequency response is shown in figure 15: figure 14. highpass filter set for 1mhz figure 15. baseband frequency response baseband frequency (mhz) ?6 amplitude (db) ?4 ?2 0 ?5 ?3 ?1 100 200 300 400 9013 f15 500 500 150 250 350 450 v cc2 3.3v v cc1 5v gain_q 0.01f 0.01f 15nh 0.01f 0.01f 15nh gnd lo in 15nh 15nh 6.8pf 100 100 100 5v gain_i v dd 1.8v ltm9013 adc adc gnd 9013 f14 clkout sdosdi sck cs adc clk ov dd 1.8v of 100 5v 6.8pf 0 90 par/ ser lna
ltm9013 28 9013f for more information www.linear.com/ltm9013 applications information figure 16. highpass filter set for 55mhz figure 17. baseband frequency response for those applications that require a higher frequency corner at the highpass point, the network can be tailored, for example, as shown in figure 16. the typical performance for the overall module is shown below: if passband (1.0db): 55mhz to 315mhz rf input for C1dbfs: C5dbm at maximum gain snr at C1dbfs: 59.1db hd2 at C1dbfs: 74dbc imd3 at C7dbfs per tone: C72dbc the frequency response is shown in figure 17: baseband frequency (mhz) ?3.0 amplitude (db) ?2.0 ?1.0 0 ?2.5 ?1.5 ?0.5 100 200 300 400 9013 f17 500 500 150 250 350 450 v cc2 3.3v v cc1 5v gain_q 0.01f 0.01f 0.01f 0.01f gnd lo in 56pf 56pf 180nh 56pf 56pf 180nh 150nh 150nh 100 100 100 5v gain_i v dd 1.8v ltm9013 adc adc gnd 9013 f16 clkout sdosdi sck cs adc clk ov dd 1.8v of 100 5v 0 90 par/ ser lna
ltm9013 29 9013f for more information www.linear.com/ltm9013 supply sequencing the v cc1 pins supply voltage to the demodulator. the v cc2 pins supply voltage to the amplifiers. the amplifier output stages are also fed by the v cc1 pins, so careful power supply sequencing is important. power must be applied to the v cc2 pins before power is applied to the v cc1 pins to avoid damage to the amplifiers. note also that the amplifiers must be enabled before voltage is applied to the v cc1 pins for the same reason. grounding and bypassing the ltm9013 requires a printed circuit board with a clean unbroken ground plane; a multilayer board with an internal ground plane is recommended. the pinout of the ltm9013 has been optimized for a flowthrough layout so that the interaction between inputs and digital outputs is minimized. a continuous row of ground pads facilitate a layout that ensures that digital and analog signal lines are separated as much as possible. the ltm9013 is internally bypassed with the adc (v dd ), mixer, amplifier (v cc ) digital (ov dd ) supplies returning to a common ground (gnd). additional bypass capacitance is optional and may be required if power supply noise is significant. heat transfer most of the heat generated by the ltm9013 is transferred through the bottom-side ground pins. for good electrical and thermal performance, it is critical that all ground pins are connected to a ground plane of sufficient area with as many vias as possible. recommended layout the high integration of the ltm9013 makes the pcb board layout simple. however, to optimize its electrical and thermal performance, some layout considerations are still necessary. ? use large pcb copper areas for ground. this helps to dissipate heat in the package through the board and also helps to shield sensitive on-board analog signals. ? use multiple ground vias. using as many vias as pos - sible helps to improve the thermal performance of the board and creates necessary barriers separating analog and digital traces on the board at high frequencies. ? separate analog and digital traces as much as possible, using vias to create high frequency barriers. this will reduce digital feedback that can reduce the signal-to- noise ratio (snr) and dynamic range of the ltm9013. figures 18 through 25 give a good example of the recom - mended layout. the quality of the paste print is an important factor in producing high yield assemblies. it is recommended to use a type 3 or 4 printing no-clean solder paste. the solder stencil design should follow the guidelines outlined in pcb assembly and manufacturing guidelines bga packages: assembly considerations for linear tech - nology module bga packages. applications information
ltm9013 30 9013f for more information www.linear.com/ltm9013 typical applications figure 18. schematic for recommended layout ip2 adjust disable parallel 3.5 ma ip2 adjust enable cl ock duty stabilize on amp run cl ock duty stabilize off cl k_in i/q enable lo_in run ga in a djust (i ch) amp_mute (hi) rf_in amp s hutdown 1.75 ma i/q di sa ble sleep serial ga in a djust ( q ch) demod r ef ip2 adjust (q ch) ip2 adjust (i ch) matc hed for 1.95ghz matc hed for 1.8ghz vcc1_load db89+ db67- db01- vdd da 121 3- da45- da89- da 101 1+ db 101 1- da89+ clkout- da 121 3+ clkout+ ~cs ~amp_shdn vcc2 da23+ da23- db 101 1+ db67+ db01+ db89- da67+ db23- of- vcc1 da01+ db23+ sdo db 121 3- sdi da 101 1- db45- da67- db45+ da01- of+ da45+ db 121 3+ sck vdd vcc2 vcc2 vcc1 vcc1 vcc2 vcc1 vdd vdd vcc2 vdd vdd vdd vcc1_load vcc1 vcc1 vdd vcc2 vcc1_load c5 0.01uf c6 0.01uf jp2 1 2 3 c17 2.2uf r20 0 r30 1.74k r35 0 r6 3.83k c7 0.01uf r26 49.9 j1 c27 dni r14 100 c15 0.1uf c26 0.01uf c12 0.1uf r34 1k r33 178 r21 1k j3 r9 10k jp3 1 2 3 e5 c4 6.8pf r5 100 jp1 1 2 3 r39 0 r18 0.1 r2 1k jp5 1 2 3 e4 r23 1.74k c20 1.5pf r12 3.83k c11 0.01uf r36 dni c8 dni j2 e6 jp4 1 2 3 r19 0.1 jp7 1 2 3 r22 100 c18 2.2uf c10 6.8pf r28 178 r1 1k r17 0.1 c3 dni t2 m aba0 071 59 5 3 1 4 u2 ltm9013 b5 b3 a3 b1 f5 d3 d2 c2 c9 a10 a11 a12 a13 c10 c1 f2 f11 f12 g13 h3 h1 h12 a14 b10 b11 b12 b13 b14 m1 e8 c3 c4 e11 g4 g1 f7 h7 g10 g9 c12 c13 c14 h5 h8 h10 g3 d5 k5 f6 a9 a8 a7 a6 d12 d13 d14 e1 a5 a2 a1 e5 l5 j12 j14 e9 e10 j11 h13 k13 e14 f1 h6 f3 f4 j13 k2 l8 m5 f9 m2 m7 m6 m11 m10 n8 g2 n9 n10 p14 p10 p9 p8 p7 p5 p6 p2 g14 b2 b4 h4 b6 b7 b8 b9 h9 c5 c6 c7 c8 h14 c11 d1 j3 j4 d4 d7 d8 d9 d10 d11 e2 e3 e4 e7 k1 e12 k3 k4 k6 d6 f8 f10 k9 k10 f13 f14 e13 k14 g5 g6 g7 g8 l6 e6 g11 g12 l9 l10 l11 l12 l13 l14 a4 h11 m3 n1 j1 j2 j5 j6 j7 j8 j10 m12 m13 m14 k7 k8 k11 k12 l1 l2 l3 l4 l7 n11 n12 n13 n14 m8 m9 p3 p4 n2 n3 n4 n5 n6 n7 p11 p12 p13 p1 h2 j9 m4 gnd gnd gain_q vcc2 gnd gnd gnd gnd gnd of- db01- db23- db67- gnd vcc2 gnd gnd gnd gnd gnd gnd gnd gnd of+ db01+ db23+ db67+ db 121 3+ vcc2 gnd en#_q shdn#_q gnd gnd gnd gnd gnd gnd gnd db45- db89- db 121 3- gnd gnd gnd gnd +in_q +in_i gnd gnd gnd gnd gnd db45+ db89+ db 101 1+ lo- gnd gnd gnd -i n_q -i n_i gnd gnd clk+ clk- gnd gnd ovdd db 101 1- lo+ gnd nc eip2 gnd gnd gnd gnd vdd gnd gnd gnd gnd gnd gnd vcc1 gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd clkout- gnd gnd ref gnd gnd gnd gnd sense gnd gnd gnd gnd clkout+ gnd gnd nc nc gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd rf gnd ip2_i ip2_q +out_i +out_q gnd gnd par_ser# cs# gnd gnd ovdd da23+ gnd gnd gnd gnd -out_i -out_q gnd gnd sck sdi sdo da89- da45- da23- vcc2 gnd gain_i vcc2 gnd gnd gnd gnd gnd gnd gnd da89+ da45+ da01+ gnd gnd gnd gnd gnd gnd gnd gnd gnd da 121 3- da 101 1- da67- da01- gnd gnd en#_i shdn#_i gnd gnd gnd gnd gnd gnd da 121 3+ da 101 1+ da67+ gnd en vdd vcc2 c22 6.8nh r24 1k e3 r11 0 c9 dni l5 3.3nh r7 1.00k c23 0.01uf r3 1k r10 1k c14 0.1uf r8 100 r15 1.00k l1 15nh c2 dni r31 1.00k c24 0.5pf c19 100pf l4 15nh l3 15nh r37 49.9 u1 si1563dh 6 2 1 3 4 5 c1 0.01uf r16 0.1 r29 1.58k r13 1k c16 0.01uf r32 1k e1 r38 dni c13 0.1uf e2 c25 0.01uf t1 bd0826j50200a00 1 2 3 4 5 6 jp6 1 2 3 r4 1k c21 dni l2 15nh r27 1k r25 1.00k
ltm9013 31 9013f for more information www.linear.com/ltm9013 typical applications figure 19. additional schematic elements for recommended layout +5v gnd eep rom w rite en +5v in d is +3.3v +1.8v +5v_in db67+ sdi vcc1 da45- da89- da01+ db1011- sck sda db45- sdo da45+ da1011+ da67+ db1011+ clkout- sda of- db01- vdd da23- db1213- da23+ db89+ db23+ clkout+ da01- da1213+ vcc2 da1213- db67- scl ~cs db89- da67- db45+ db1213+ db01+ db23- da89+ of+ scl da1011- ~amp_shdn vdd vcc2 vcc1 c36 0.1uf u4 lt3080edd 7 5 3 8 2 1 9 4 vin vctrl vout vin vout vout pad set c38 0.1uf r44 10k + c29 47uf c31 4.7uf u8 fmc_mounting_hole gnd + c32 47uf r42 3k jp8 1 2 3 r47 1k u9 fmc_mounting_hole gnd u10 fmc_mounting_hole gnd j4h seam-10x40pin h1 h2 h3 h4 h5 h6 h7 h8 h9 h10 h11 h12 h13 h14 h15 h16 h17 h18 h19 h20 h21 h22 h23 h24 h25 h26 h27 h28 h29 h30 h31 h32 h33 h34 h35 h36 h37 h38 h39 h40 vref_a_m2c prsnt_m2c_n gnd clk0_m2c_p clk0_m2c_n gnd la02_p la02_n gnd la04_p la04_n gnd la07_p la07_n gnd la11_p la11_n gnd la15_p la15_n gnd la19_p la19_n gnd la21_p la21_n gnd la24_p la24_n gnd la28_p la28_n gnd la30_p la30_n gnd la32_p la32_n gnd vadj r45 10k u7 si1563dh 6 2 1 3 4 5 c33 0.1uf j4d seam-10x40pin d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 d16 d17 d18 d19 d20 d21 d22 d23 d24 d25 d26 d27 d28 d29 d30 d31 d32 d33 d34 d35 d36 d37 d38 d39 d40 pg_c2m gnd gnd gbtclk0_m2c_p gbtclk0_m2c_n gnd gnd la01_p_cc la01_n_cc gnd la05_p la05_n gnd la09_p la09_n gnd la13_p la13_n gnd la17_p_cc la17_n_cc gnd la23_p la23_n gnd la26_p la26_n gnd tck tdi tdo 3p3vaux tms trst_n ga1 3p3v gnd 3p3v gnd 3p3v u5 24lc 32a-i /st 1 2 3 4 5 6 7 8 a0 a1 a2 vss sda scl wp vcc r40 3k u6 fmc_mounting_hole gnd j4g seam-10x40pin g1 g2 g3 g4 g5 g6 g7 g8 g9 g10 g11 g12 g13 g14 g15 g16 g17 g18 g19 g20 g21 g22 g23 g24 g25 g26 g27 g28 g29 g30 g31 g32 g33 g34 g35 g36 g37 g38 g39 g40 gnd clk0_c2m_p clk0_c2m_n gnd gnd la00_p_cc la00_n_cc gnd la03_p la03_n gnd la08_p la08_n gnd la12_p la12_n gnd la16_p la16_n gnd la20_p la20_n gnd la22_p la22_n gnd la25_p la25_n gnd la29_p la29_n gnd la31_p la31_n gnd la33_p la33_n gnd vadj gnd r46 10k c37 0.1uf j4c seam-10x40pin c1 c2 c3 c4 c5 c6 c7 c8 c9 c10 c11 c12 c13 c14 c15 c16 c17 c18 c19 c20 c21 c22 c23 c24 c25 c26 c27 c28 c29 c30 c31 c32 c33 c34 c35 c36 c37 c38 c39 c40 gnd dp0_c2m_p dp0_c2m_n gnd gnd dp0_m2c_p dp0_m2c_n gnd gnd la06_p la06_n gnd gnd la10_p la10_n gnd gnd la14_p la14_n gnd gnd la18_p_cc la18_n_cc gnd gnd la27_p la27_n gnd gnd scl sda gnd gnd ga0 12p0v gnd 12p0v gnd 3p3v gnd c30 4.7uf r43 182k e7 r50 10k r49 10k + c35 47uf u3 lt3080edd 7 5 3 8 2 1 9 4 vin vctrl vout vin vout vout pad set r41 330k r48 10k c34 0.1uf e8
ltm9013 32 9013f for more information www.linear.com/ltm9013 typical applications figure 20. layer 1 figure 21. layer 2
ltm9013 33 9013f for more information www.linear.com/ltm9013 typical applications figure 22. layer 3 figure 23. layer 4
ltm9013 34 9013f for more information www.linear.com/ltm9013 typical applications figure 24. layer 5 figure 25. layer 6
ltm9013 35 9013f for more information www.linear.com/ltm9013 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package description please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. package top view 4 pin ?a1? corner y x aaa z aaa z package bottom view bga package 196-lead (15mm 15mm 2.82mm) (reference ltc dwg# 05-08-1907 rev ?) notes: 1. dimensioning and tolerancing per asme y14.5m-1994 2. all dimensions are in millimeters ball designation per jesd ms-028 and jep95 4 3 details of pin #1 identifier are optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or marked feature detail a ?b (196 places) detail b substrate a a1 b1 ccc z detail b package side view mold cap z m x yzddd m zeee symbol a a1 a2 b b1 d e e f g h1 h2 aaa bbb ccc ddd eee min 2.62 0.40 2.22 0.55 0.55 0.22 1.95 nom 2.82 0.50 2.32 0.60 0.60 15.0 15.0 1.0 13.0 13.0 0.32 2.00 max 3.02 0.60 2.42 0.65 0.65 0.42 2.05 0.15 0.10 0.15 0.15 0.08 notes dimensions total number of balls: 196 a2 d e suggested pcb layout top view 0.00 4.50 2.50 6.50 5.50 3.50 6.50 4.50 5.50 1.50 0.50 2.50 0.50 3.50 1.50 5.50 2.50 1.50 3.50 4.50 2.50 1.50 0.50 0.50 6.50 5.50 6.50 4.50 3.50 0.00 6.20 6.80 // bbb z z h2 h1 5. primary datum -z- is seating plane 6. solder ball composition is 96.5% sn/3.0% ag/0.5% cu 0.60 0.025 ? 196x p n m l k j h g f e d c b a 123456 14 13 12 11 10 9 8 7 detail a 3 see notes pin 1 e e f g b 6.80 6.20 bga 196 0911 rev ? tray pin 1 bevel package in tray loading orientation component pin ?a1? ltmxxxxxx module
ltm9013 36 9013f for more information www.linear.com/ltm9013 ? linear technology corporation 2013 lt 0313 ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/ltm9013 related parts typical application rms detection 1mhz bpf dsp dac adc ip2i ltm9013 f lo = 1990mhz f1 = 20mhz f2 = 21mhz 9013 ta02 lna loopback ltc5588-1 1-d minimization algorithm dac pa + block diagram for im2 adjustment. only the i-channel is shown part number description comments adcs ltc2208 16-bit, 130msps, 3.3v adc, lvds outputs 1250mw, 77.7db snr, 100db sfdr, 64-lead qfn package ltc2157-14/ ltc2156-14/ ltc2155-14 14-bit, 250msps/210msps/170msps, 1.8v dual adc, ddr lvds outputs 605mw/565mw/511mw, 70db snr, 90db sfdr, 9mm 9mm 64-lead qfn package ltc2152-14/ltc2151-14/ ltc2150-14 14-bit, 250msps/210msps/170msps, 1.8v single adc, ddr lvds outputs 338mw/316mw/290mw, 70db snr, 90db sfdr, 6mm 6mm 40-lead qfn package ltc2158-14 14-bit, 310msps 1.8v dual adc, ddr lvds outputs, low power 724mw, 68.8db snr, 88db sfdr, 9mm 9mm 64-lead qfn package rf mixers/demodulators lt5517 40mhz to 900mhz direct conversion quadrature demodulator high iip3: 21dbm at 800mhz, integrated lo quadrature generator lt5527 400mhz to 3.7ghz high linearity downconverting mixer 24.5dbm iip3 at 900mhz, 23.5dbm iip3 at 3.5ghz, nf = 12.5db, 50 single-ended rf and lo ports LT5575 800mhz to 2.7ghz direct conversion quadrature demodulator high iip3: 28dbm at 900mhz, integrated lo quadrature generator, integrated rf and lo transformer amplifiers/filters ltc6409 10ghz gbw, 1.1 nv/ hz differential amplifier/adc driver 88db sfdr at 100mhz, input range includes ground 52ma supply current, 3mm 2mm qfn package ltc6412 800mhz, 31db range, analog-controlled variable gain amplifier continuously adjustable gain control, 35dbm oip3 at 240mhz, 10db noise figure, 4mm 4mm qfn-24 package ltc6420-20 1.8ghz dual low noise, low distortion differential adc drivers for 300mhz if fixed gain 10v/v, 1nv/ hz total input noise, 80ma supply current per amplifier, 3mm 4mm qfn-20 package receiver subsystems ltm9002 14-bit dual channel if/baseband receiver subsystem integrated high speed adc, passive filters and fixed gain differential amplifiers ltm9003 12-bit digital pre-distortion receiver integrated 12-bit adc down-converter mixer with 0.4ghz to 3.8ghz input frequency range

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